Hardware Acceleration for BDD manipulations

نویسندگان

  • Tomohiro Yoneda
  • Takeshi Ishigaki
چکیده

In this paper, in order to accelerate BDD based algorithms, we propose implementing BDD operations by hardware. We have designed a RTL model of the proposed hardware, and expressed it by C language so that we can count the number of clocks needed for each BDD operation. We have examined its performance improvement with respect to the original software library by using several benchmark circuits.

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

MINCE: A Static Global Variable-Ordering for SAT Search and BDD Manipulation

The increasing popularity of SAT and BDD techniques in formal hardware verification and automated synthesis of logic circuits encourages the search for additional speed-ups. Since typical SAT and BDD algorithms are exponential in the worst-case, the structure of real-world instances is a natural source of improvements. While SAT and BDD techniques are often presented as mutually exclusive alter...

متن کامل

BDD Package Based on Boolean NOR Operation

Binary Decision Diagrams (BDDs) are useful data structures for symbolic Boolean manipulations. BDDs are used in many tasks in VLSI/CAD, such as equivalence checking, property checking, logic synthesis, and false paths. In this paper we describe a new approach for the realization of a BDD package. To perform manipulations of Boolean functions, the proposed approach does not depend on the recursi...

متن کامل

MINCE: A Static Global Variable-Ordering Heuristic for SAT Search and BDD Manipulation

The increasing popularity of SAT and BDD techniques in formal hardware verification and automated synthesis of logic circuits encourages the search for additional speedups. Since typical SAT and BDD algorithms are exponential in the worst-case, the structure of realworld instances is a natural source of improvements. While SAT and BDD techniques are often presented as mutually exclusive alterna...

متن کامل

Combinatorial Logic Circuitry as Means to Protect Low Cost Devices Against Side Channel Attacks

In this paper we present a clock frequency watch dog that can be realized using a digital standard CMOS library. Such watch dog is required to prevent clock speed manipulations that can support side channel attacks on cryptographic hardware devices. The additional area and power consumed by the watch dog for an AES hardware accelerator are 4,200μm and 2nJ per 128 bit respectively. The physical ...

متن کامل

Advances in Functional Decomposition: Theory and Applications

Functional decomposition aims at finding efficient representations for Boolean functions. It is used in many applications, including multi-level logic synthesis, formal verification, and testing. This dissertation presents novel heuristic algorithms for functional decomposition. These algorithms take advantage of suitable representations of the Boolean functions in order to be efficient. The fi...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2007